HLX (HF Luminosity)

This version of the "sandwich board" will be used for the HF luminosity. It sits on a single SLB site, and has the ethernet phy chip for output to a CPU. See "above" URL for schematics and design files.

Click here to go to the HLX cookbook.

Registers for the HLX FPGA (Virtex VP20/Princeton Version)

Notes:

Address is 7 bits [6:0]. To address the VP20, at least one of the upper 3 bits must be nonzero

Address	Bits	Name	R/W	Comments
0x10	16	CntrReg	RW	Control register, bits are: Bit 0 = level, can use this for VME setting of the 2 differential outputs as a level (VME_LVDSout) Bit 1 = enable histogramming Bit 2 = for zeroing histograms after reading Bit 3 = mux to blink LED whenever the "BC0" arrives (to check that it's actually arriving) Bit 8:4 = select histogram reading (0=tower enables, 1,2,3 are the occupancy histograms, 4 is the sumET) Bit 9 = N/A Bit 10 = Ethernet packet length override (see 0x73)
0x11	16	Test	R	Should be 'hFFFFF
0x12	16	Test	R	Should be 'h0
0x13	16	Firmware Version	R	Should be 0x7nnn where nnn is the revision number (7 means "test")
0x14	8	Mux	RW	Version 5 or after, for muxing stuff onto LA (see code for details)
0x15	16	Status Reg	R	Status register, bits are: Bit 0 = RxDLL lock Bit 1 = run status Bit 2 = Bunch Error Bit 3 = TTC_DLL_lock (comes from the DCM which deals with the "TTC" clock from the TTCrx) Bit 4 = histogramming complete (cleared after histograms have been filled) Bit 5 = ethernet packet sent and packet number incremented (and ready for next one, if you wait long enough!) Bits 10:8 = counter to reset DCM for the TTC stuff
0x16	16	UDP port DEST #	RW	16-bit UDP port DESTINATION number. Default =0, MUST be set!!!!
0x17	17	UDP port SRC #	RW	16-bit UDP port SOURCE number. \| Default =0, MUST be set!!!!
0x18	8	LastTTCcommand	R	The last TTC command seen
0x20-2F	16	TTC test	R	Counts how many times we have seen TTC command 0-F
0x30-0x33	12	Nonz counter	R	Counts number of buckets between BC0 and first non-zero value of sum0 (0x30), sum1(0x31), etc. "sum0" means the sum over channels for bit pattern 2'b00 on the channel input code. After reading any of these 4 registers you have to clear via 0x61 bit 6.
0x35-0x37	12/13	SpyFIFO 1	R	Read 1st, 2nd, and 3rd 12 bits of data plus fifo empty (MSB) from TPG set 1. The first read (0x35) causes a latch of the entire 36 bits after the fifo read.
0x38-0x3A	12/13	SpyFIFO 2	R	Same as above for the 2nd fifo (TPG set 2).
0x3B-0x3D	12/13	SpyFIFO 3	R	Same as above for the 3nd fifo (the 4 sums on the TOP).
0x3E	16	RXClk cnt	R	Counts clocks from RX_CLK since last soft reset if run status is START
0x40	16	RXBC0 cnt	R	Counts number of RX_BC0 seen
0x44	8	TTC BC0 pattern	RW	Sets the TTC broadcast pattern that the HLX will use to mean "BC0" (8 bits, but remember that bits 4,2,1,0 are reserved. A common pattern is 0x20, and that would cause "pattern 2", register 0x22, to increment.)

0x50	12	Hist bin	RW	Bin to read histogram from (0 to 3563 only). Set this first, then read from one of the 4 registers 0x51,0x52,0x53,0x54,0x55
0x51	16	Hist0 read	R	Read 16-bits of histogram 0 from bin set via register 0x50
0x52	16	Hist1 read	R	Read 16-bits of histogram 1 from bin set via register 0x50
0x53	16	Hist2 read	R	Read 16-bits of histogram 2 from bin set via register 0x50
0x54	16	Hist3 read	R	Read 16-bits of histogram 3 from bin set via register 0x50
0x55	16	HistSUM read	R	Read 16-bits of histogram sumET from bin set via register 0x50
0x61	16	WriteOnlyCntrReg	W	Write only control register, bits are: Bit 0 = Hard reset Bit 1 = Start Bit 2 = Stop Bit 3 = Soft reset Bit 4 = N/A Bit 5 = VME_LVDSout pulse (see above if you want to use this as a level) Bit 6 = Reset the counters of #buckets between BC0 and nonzero sums (see 0x30-0x33) Bit 7 = Ethernet packet reset (reset to packet 0) Bit 8 = Send next ethernet packet
0x62	16	Dest MAC addr 1	RW	Low 16 bits of destination MAC address
0x63	16	Dest MAC addr 2	RW	Middle 16 bits of destination MAC address
0x64	16	Dest MAC addr 3	RW	High 16 bits of destination MAC address
0x65	16	Src MAC addr 1	RW	Low 16 bits of source MAC address (the HLX is the "source")
0x66	16	Src MAC addr 2	RW	Middle 16 bits of source MAC address (the HLX is the "source")
0x67	16	Src MAC addr 3	RW	High 16 bits of source MAC address (the HLX is the "source")
0x70	3	Histogram Select	RW	This selects histogram 0-4 (0-3 are occupancy, 4 is sumET) to transmit over ethernet (version 7010 and higher).
0x71	3	Packet pointer	R	This is the next packet that would be sent
0x72	11	Byte Count	R	1/4 number of bytes sent by the ethernet stuff, per packet. Should make sense.
0x73	11	Packet Length	RW	Ethernet packet length (set CSR bit 10 to override defaults for histogram sending, this is for debugging only)
0x74	4	BC0 Delay	RW	Delay for BC0 to account for internal delays inside HTR and HLX of the data (only valid for HLX versions 17 and higher)
0x75	16	Source IP (low)	RW	Low 16 bits of 32 bit source IP address
0x76	16	Source IP (high)	RW	High 16 bits of 32 bit source IP address
0x77	16	Dest IP (low)	RW	Low 16 bits of 32 bit destination IP address
0x78	16	Dest IP (high)	RW	High 16 bits of 32 bit destination IP address

Registers for the HLX CPLD (only on the Princeton version of the HLX board)

Notes:

Localbus address is 7 bits [6:0]. To address the CPLD, all of the top 3 bits must be identically zero (LOCADD[6:4] == 0)

Address	Bits	Name	R/W	Comments
0x0	8	Version	R	Version number
0x1	3	Mux	R/W	Mux for debugging. This selects what to put onto the 2 LEDs, which you can pick up with a scope or LA. Default is 0, which puts a ~1sec clock and the FLASH RST pin out
0x2	8	Status	R	Status bits. The most important is bit 5 (Status[5]), which is the flash "RDY" bit. You can poll this bit to know that the flash erase has finished (which usually takes 10 sec)
0x3	0	Reset Add	W	Reset the internal 20-bit address to zero
0x4	0	Inc Add	W	Increment the internal 20-bit address (not needed for normal operation)
0x5	8	Read Add	R	Read the lower byte of the internal 20-bit address (for debugging)
0x6	0	Flash Reset	W	Resets the flash by driving the M_RST line low for ~400 ns or so
0x7	8	Flash Read	R	Reads the value of the flash pointed to by the internal 20-bit address
0x8	8	Flash Write	W	Write this byte to the flash using the 20-bit internal address for the flash address. Note: after this write, the CPLD will automatically increment the address.
0x9	8	Flash Write555	W	Write this byte to the flash using address 'h555 (this is 1 of 2 control addresses)
0xA	8	Flash Write AAA	W	Write this byte to the flash using address 'hAAA (this is 1 of 2 control addresses)

Firmware

For the HTR, special purpose firmware to talk to this board at 80MHz over SLB/TPG lines:

(Note: As of Sept 2006, this is no longer needed. The firmware to use will be “regular” HF HTR firmware. Please see the usual firmware depository)

Luminosity HTR	File to load	FPGAversionN	Notes
HTRev4_v7002.zip	HTRev4_v7002.mcs	0x70002	Firmware in HTR, equivalent to HTR version 0x25
HTRev4_v7003.zip	HTRev4_v7003.mcs	0x70003	Built from v70002. Reset 'tcount' to zero when TTC_TestEnable is asserted, and send TTC_TestEnable instead of L1A (debugging)
HTRev4_v7004.zip	HTRev4_v7014.mcs	0x70014	Built from v70003. No longer use the TPG LUT, since we will need to keep that for HF. Add 2 new registers for digital thresholds setable via VME (0x1B0 for low and 0x1B4 for high), and cut on the linearized energy after summing over 2 time slices. Also add a spy fifo for the linearized 10-bit value from the 1st ("input") LUT for channel 1. The fifo read address 0x1B8. Also add a register to "mux" 1 of 24 channels at 1BC.
HTRev4_v7005.zip	HTRev4_v7005.mcs	0x70005	Built from v70004, hook up all 8 fibers to the TPG output
HTRev4_v7006.zip	HTRev4_v7006.mcs	0x70006	Built from v70005, in progress, will contain the sumET calculation transmission to the HLX (use HLX v14 or above for that)
HTRev4_v7007.zip	HTRev4_v7007.mcs	0x70007	Built from v70006, but has a way of injecting fake data without using the fiber inputs or the RAMS. You do this via the ./htr/HLX/FAKE command. I use CSR bit 0, formerly for "histogram mode" but now obsolete. There's also an offset at localbus address 0x200. if CSR 0 is set, then the HTR will send code 01 for all channels except at the bucket number which the offset points to, and then it'll send code 11. The HTR will use TTC broadcast code 0x20 (TTCtestenable) as the BC0.
HTRev4_v7008.zip	HTRev4_v7008.mcs	0x70008	Same as above but the HLX has to be on the bottom (6th) SLB site (the above versions had the HLX on the top, or first, SLB site).

Firmware for the HLX Virtex FPGA:

Luminosity HFX	File to load	FPGAversionN	Notes
HLX_v7001.zip	HLX_v7001.bit HLX_v7001.mcs	0x7001	Formerly called the "Sandwich" board, this is now known as the HLX and is a mezzanine card sitting on an SLB site for the HF luminosity project
HLX_v7002.zip	HLX_v7002.bit HLX_v7002.mcs	0x7002	Built from 0x7001 but includes sending output to Wisconsin pads (see below)
HLX_v7003.zip	HLX_v7003.bit HLX_v7003.mcs	0x7003	Built from 0x7002, remapping of names for data so it's easier to use, and check that the TTC_CK posedge is in the middle of the data - it is!
HLX_v7004.zip	HLX_v7004.mcs	0x7004	Built from 0x7003. Add ability to read out spy fifos. There are 2 spy fifo's, each one 36 bits, for the TOP and BOT. Readout is via 3 via commands, 12 bits on each readout with a fifo read enable on the 1st. See the verilog code, and also the code for "HLX" menu in htr.cc
HLX_v7005.zip	HLX_v7045.mcs	0x7045	Built from 0x7004. Fix the timing, get it right for QIE1-3.
HLX_v7006.zip	HLX_v7036.mcs	0x7036	Built from 0x7005. Add summing over the 4 levels for 24 channels (only TOP so far...)
HLX_v7008.zip	HLX_v7048.mcs	0x7048	Built from 0x7006. Fix up clocking (DCM) and etc....
HLX_v7009.zip	HLX_v7049.mcs	0x7049	Built from 0x7008. More clocking fixes, this version (I hope!) has all the clocking right so that when we add the histograms, any errors should be these new modules.
HLX_v700a.zip	HLX_v709a.mcs	0x709a	Built from 0x7009. This is the first pass on the histograms. Histograms are filled correctly, but the timing for the readout is probably off. Next version should fix it.
HLX_v700b.zip	HLX_v706b.mcs	0x706b	OK, this one appears to work. It's not pretty, but so far so good. A few things left to test, but it does all 4 of the level histograms (but not the sumET one). Works with v5 of HTR above.
HLX_v700d.zip	HLX_v700d.mcs	0x700d	Rewrite of 0x706b so that it's easier to control. This one should be integrated with Professor Mans' ethernet technology.
HLX_v700f.zip	HLX_v730f.mcs	0x700f	This includes the sumET histograms (squeezed down to 6 bits) and should be used with v7006 of the HTR firmware.
HLX_v7013.zip	HLX_v7813.mcs	0x7813	First firmware that successfully sends out ethernet packets, 7 to a histogram, all manually controllable via VME (see below)
HLX_v7816.zip	HLX_v7816.mcs	0x7816	Rewrite of some of it - now there is block ram that I write histogram packets into, the Jeremy reads and sends out to ethernet. Ethernet works, histograms are transmitted correctly, all is good. This works with version HTRev4_v7007 above.
HLX_v7017.zip	HLX_v7017.mcs	0x7917	Add 32-bit source and destination IP address registers (0x75-0x78), and digital BC0 offset register (0x74)
HLX_v7018.zip	HLX_v7018.mcs	0x7018	Same as above, but Jeremy changes it from TCP to UDP. Note: still only looks at the TOP part of the HTR, but uses all 24 channels, and since the HF HTRs will now have long + short fibers, the version we will finally use will be TOP(12)+BOT(12) or 24 anyway. Next version will have the change. Jeremy’s latest version of the software to capture packets is here.

STATUS
- 18 Mar 05: received 2+ boards assembled by Compunetix; verified LocalBus, TTC, spy of data, clocks and BC0s from HTR; LVDS outputs seem ok on a scope.

Drew Baden 9/11/06

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