| Property | Value |
| Project Name: | c:\cms\firmware\luminosity\htr\v7 |
| Target Device: | xc2v3000 |
| Report Generated: | Friday 02/24/06 at 10:48 |
| Printable Summary (View as HTML) | top_summary.html |
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Total Number Slice Registers: | 8,273 | 28,672 | 28% | |
| Number used as Flip Flops: | 8,263 | |||
| Number used as Latches: | 10 | |||
| Number of 4 input LUTs: | 13,208 | 28,672 | 46% | |
| Logic Distribution: | ||||
| Number of occupied Slices: | 10,993 | 14,336 | 76% | |
| Number of Slices containing only related logic: | 10,993 | 10,993 | 100% | |
| Number of Slices containing unrelated logic: | 0 | 10,993 | 0% | |
| Total Number 4 input LUTs: | 16,614 | 28,672 | 57% | |
| Number used as logic: | 13,208 | |||
| Number used as a route-thru: | 1,076 | |||
| Number used for 32x1 RAMs: | 2,112 | |||
| Number used as Shift registers: | 218 | |||
| Number of bonded IOBs: | 486 | 684 | 71% | |
| Number of Block RAMs: | 96 | 96 | 100% | |
| Number of GCLKs: | 8 | 16 | 50% | |
| Number of DCMs: | 1 | 12 | 8% |
| Property | Value |
| Final Timing Score: | 0 |
| Number of Unrouted Signals: | All signals are completely routed. |
| Number of Failing Constraints: | 0 |
| Constraint(s) | Requested | Actual | Logic Levels |
| All Constraints Met |
| Report Name | Status | Last Date Modified |
| Synthesis Report | Current | Friday 02/24/06 at 10:34 |
| Translation Report | Current | Friday 02/24/06 at 10:35 |
| Map Report | Current | Friday 02/24/06 at 10:36 |
| Pad Report | Current | Friday 02/24/06 at 10:45 |
| Place and Route Report | Current | Friday 02/24/06 at 10:45 |
| Post Place and Route Static Timing Report | Current | Friday 02/24/06 at 10:46 |
| Bitgen Report | Current | Friday 02/24/06 at 10:48 |