| Property | Value |
| Project Name: | c:\cms\firmware\luminosity\sandwich\v9 |
| Target Device: | xc2vp7 |
| Report Generated: | Saturday 08/13/05 at 15:13 |
| Printable Summary (View as HTML) | SandwichTop_summary.html |
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Total Number Slice Registers: | 1,908 | 9,856 | 19% | |
| Number used as Flip Flops: | 1,844 | |||
| Number used as Latches: | 64 | |||
| Number of 4 input LUTs: | 1,764 | 9,856 | 17% | |
| Logic Distribution: | ||||
| Number of occupied Slices: | 1,884 | 4,928 | 38% | |
| Number of Slices containing only related logic: | 1,884 | 1,884 | 100% | |
| Number of Slices containing unrelated logic: | 0 | 1,884 | 0% | |
| Total Number 4 input LUTs: | 2,315 | 9,856 | 23% | |
| Number used as logic: | 1,764 | |||
| Number used as a route-thru: | 551 | |||
| Number of bonded IOBs: | 163 | 248 | 65% | |
| Number of PPC405s: | 0 | 1 | 0% | |
| Number of Block RAMs: | 19 | 44 | 43% | |
| Number of GCLKs: | 6 | 16 | 37% | |
| Number of DCMs: | 1 | 4 | 25% | |
| Number of GTs: | 0 | 8 | 0% | |
| Number of GT10s: | 0 | 0 | 0% |
| Property | Value |
| Final Timing Score: | 0 |
| Number of Unrouted Signals: | All signals are completely routed. |
| Number of Failing Constraints: | 0 |
| Constraint(s) | Requested | Actual | Logic Levels |
| All Constraints Met |
| Report Name | Status | Last Date Modified |
| Synthesis Report | Current | Saturday 08/13/05 at 15:11 |
| Translation Report | Current | Saturday 08/13/05 at 15:11 |
| Map Report | Current | Saturday 08/13/05 at 15:11 |
| Pad Report | Current | Saturday 08/13/05 at 15:12 |
| Place and Route Report | Current | Saturday 08/13/05 at 15:12 |
| Post Place and Route Static Timing Report | Current | Saturday 08/13/05 at 15:12 |
| Bitgen Report | Current | Saturday 08/13/05 at 15:13 |