| Property | Value |
| Project Name: | c:\cms\firmware\luminosity\htr\v5 |
| Target Device: | xc2v3000 |
| Report Generated: | Tuesday 08/09/05 at 12:50 |
| Printable Summary (View as HTML) | top_summary.html |
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Total Number Slice Registers: | 8,119 | 28,672 | 28% | |
| Number used as Flip Flops: | 8,109 | |||
| Number used as Latches: | 10 | |||
| Number of 4 input LUTs: | 12,702 | 28,672 | 44% | |
| Logic Distribution: | ||||
| Number of occupied Slices: | 10,703 | 14,336 | 74% | |
| Number of Slices containing only related logic: | 10,703 | 10,703 | 100% | |
| Number of Slices containing unrelated logic: | 0 | 10,703 | 0% | |
| Total Number 4 input LUTs: | 16,099 | 28,672 | 56% | |
| Number used as logic: | 12,702 | |||
| Number used as a route-thru: | 1,067 | |||
| Number used for 32x1 RAMs: | 2,112 | |||
| Number used as Shift registers: | 218 | |||
| Number of bonded IOBs: | 486 | 684 | 71% | |
| Number of Block RAMs: | 96 | 96 | 100% | |
| Number of GCLKs: | 8 | 16 | 50% | |
| Number of DCMs: | 1 | 12 | 8% |
| Property | Value |
| Final Timing Score: | 0 |
| Number of Unrouted Signals: | All signals are completely routed. |
| Number of Failing Constraints: | 0 |
| Constraint(s) | Requested | Actual | Logic Levels |
| All Constraints Met |
| Report Name | Status | Last Date Modified |
| Synthesis Report | Current | Tuesday 08/09/05 at 11:45 |
| Translation Report | Current | Tuesday 08/09/05 at 11:45 |
| Map Report | Current | Tuesday 08/09/05 at 11:46 |
| Pad Report | Current | Tuesday 08/09/05 at 11:57 |
| Place and Route Report | Current | Tuesday 08/09/05 at 11:57 |
| Post Place and Route Static Timing Report | Current | Tuesday 08/09/05 at 11:58 |
| Bitgen Report | Current | Tuesday 08/09/05 at 12:50 |