| Property | Value |
| Project Name: | c:\cms\firmware\luminosity\sandwich\v24 |
| Target Device: | xc2vp7 |
| Report Generated: | Wednesday 03/22/06 at 17:10 |
| Printable Summary (View as HTML) | SandwichTop_summary.html |
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Total Number Slice Registers: | 4,003 | 9,856 | 40% | |
| Number used as Flip Flops: | 3,918 | |||
| Number used as Latches: | 85 | |||
| Number of 4 input LUTs: | 5,472 | 9,856 | 55% | |
| Logic Distribution: | ||||
| Number of occupied Slices: | 4,464 | 4,928 | 90% | |
| Number of Slices containing only related logic: | 4,464 | 4,464 | 100% | |
| Number of Slices containing unrelated logic: | 0 | 4,464 | 0% | |
| Total Number 4 input LUTs: | 6,416 | 9,856 | 65% | |
| Number used as logic: | 5,472 | |||
| Number used as a route-thru: | 816 | |||
| Number used for Dual Port RAMs: | 128 | |||
| Number of bonded IOBs: | 189 | 248 | 76% | |
| Number of PPC405s: | 0 | 1 | 0% | |
| Number of Block RAMs: | 29 | 44 | 65% | |
| Number of GCLKs: | 8 | 16 | 50% | |
| Number of DCMs: | 2 | 4 | 50% | |
| Number of GTs: | 0 | 8 | 0% | |
| Number of GT10s: | 0 | 0 | 0% |
| Property | Value |
| Final Timing Score: | 0 |
| Number of Unrouted Signals: | All signals are completely routed. |
| Number of Failing Constraints: | 0 |
| Constraint(s) | Requested | Actual | Logic Levels |
| All Constraints Met |
| Report Name | Status | Last Date Modified |
| Synthesis Report | Current | Wednesday 03/22/06 at 17:05 |
| Translation Report | Current | Wednesday 03/22/06 at 17:05 |
| Map Report | Current | Wednesday 03/22/06 at 17:06 |
| Pad Report | Current | Wednesday 03/22/06 at 17:08 |
| Place and Route Report | Current | Wednesday 03/22/06 at 17:08 |
| Post Place and Route Static Timing Report | Current | Wednesday 03/22/06 at 17:08 |
| Bitgen Report | Current | Wednesday 03/22/06 at 17:10 |