Property | Value |
Project Name: | c:\cms\firmware\luminosity\sandwich\v19 |
Target Device: | xc2vp7 |
Report Generated: | Tuesday 01/03/06 at 14:44 |
Printable Summary (View as HTML) | SandwichTop_summary.html |
Logic Utilization | Used | Available | Utilization | Note(s) |
Total Number Slice Registers: | 3,685 | 9,856 | 37% | |
Number used as Flip Flops: | 3,648 | |||
Number used as Latches: | 37 | |||
Number of 4 input LUTs: | 5,243 | 9,856 | 53% | |
Logic Distribution: | ||||
Number of occupied Slices: | 4,247 | 4,928 | 86% | |
Number of Slices containing only related logic: | 4,247 | 4,247 | 100% | |
Number of Slices containing unrelated logic: | 0 | 4,247 | 0% | |
Total Number 4 input LUTs: | 6,198 | 9,856 | 62% | |
Number used as logic: | 5,243 | |||
Number used as a route-thru: | 779 | |||
Number used for Dual Port RAMs: | 176 | |||
Number of bonded IOBs: | 189 | 248 | 76% | |
Number of PPC405s: | 0 | 1 | 0% | |
Number of Block RAMs: | 28 | 44 | 63% | |
Number of GCLKs: | 9 | 16 | 56% | |
Number of DCMs: | 2 | 4 | 50% | |
Number of GTs: | 0 | 8 | 0% | |
Number of GT10s: | 0 | 0 | 0% |
Property | Value |
Final Timing Score: | 13795 |
Number of Unrouted Signals: | All signals are completely routed. |
Number of Failing Constraints: | 2 |
Constraint(s) | Requested | Actual | Logic Levels |
* TS_Tclk0 = PERIOD TIMEGRP "Tclk0" TS_TTC_CK40Des1 HIGH 50% | 24.000ns | 37.896ns | 6 |
* TS_Tclk180 = PERIOD TIMEGRP "Tclk180" TS_TTC_CK40Des1 PHASE 12 ns HIGH 50% | 24.000ns | 26.736ns | 2 |
Report Name | Status | Last Date Modified |
Synthesis Report | Current | Tuesday 01/03/06 at 14:37 |
Translation Report | Current | Tuesday 01/03/06 at 14:37 |
Map Report | Current | Tuesday 01/03/06 at 14:38 |
Pad Report | Current | Tuesday 01/03/06 at 14:42 |
Place and Route Report | Current | Tuesday 01/03/06 at 14:42 |
Post Place and Route Static Timing Report | Current | Tuesday 01/03/06 at 14:42 |
Bitgen Report | Current | Tuesday 01/03/06 at 14:44 |