Design Overview for SandwichTop

PropertyValue
Project Name:c:\cms\firmware\luminosity\sandwich\v19
Target Device:xc2vp7
Report Generated:Tuesday 01/03/06 at 14:44
Printable Summary (View as HTML)SandwichTop_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers:3,6859,85637% 
Number used as Flip Flops:3,648   
Number used as Latches:37   
Number of 4 input LUTs:5,2439,85653% 
Logic Distribution:    
Number of occupied Slices:4,2474,92886% 
Number of Slices containing only related logic:4,2474,247100% 
Number of Slices containing unrelated logic:04,2470% 
Total Number 4 input LUTs:6,1989,85662% 
Number used as logic:5,243   
Number used as a route-thru:779   
Number used for Dual Port RAMs:176   
Number of bonded IOBs:18924876% 
Number of PPC405s:010% 
Number of Block RAMs:284463% 
Number of GCLKs:91656% 
Number of DCMs:2450% 
Number of GTs:080% 
Number of GT10s:000% 

Performance Summary

PropertyValue
Final Timing Score:13795
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:2

Failing Constraints (total failing = 2)

Constraint(s)RequestedActualLogic Levels
* TS_Tclk0 = PERIOD TIMEGRP "Tclk0" TS_TTC_CK40Des1 HIGH 50% 24.000ns37.896ns6
* TS_Tclk180 = PERIOD TIMEGRP "Tclk180" TS_TTC_CK40Des1 PHASE 12 ns HIGH 50% 24.000ns26.736ns2

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentTuesday 01/03/06 at 14:37
Translation ReportCurrentTuesday 01/03/06 at 14:37
Map ReportCurrentTuesday 01/03/06 at 14:38
Pad ReportCurrentTuesday 01/03/06 at 14:42
Place and Route ReportCurrentTuesday 01/03/06 at 14:42
Post Place and Route Static Timing ReportCurrentTuesday 01/03/06 at 14:42
Bitgen ReportCurrentTuesday 01/03/06 at 14:44