Property | Value |
Project Name: | c:\cms\firmware\luminosity\sandwich\v13 |
Target Device: | xc2vp7 |
Report Generated: | Thursday 08/25/05 at 15:03 |
Printable Summary (View as HTML) | SandwichTop_summary.html |
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops: | 2,016 | 9,856 | 20% | |
Number of 4 input LUTs: | 1,894 | 9,856 | 19% | |
Logic Distribution: | ||||
Number of occupied Slices: | 1,968 | 4,928 | 39% | |
Number of Slices containing only related logic: | 1,968 | 1,968 | 100% | |
Number of Slices containing unrelated logic: | 0 | 1,968 | 0% | |
Total Number 4 input LUTs: | 2,456 | 9,856 | 24% | |
Number used as logic: | 1,894 | |||
Number used as a route-thru: | 562 | |||
Number of bonded IOBs: | 163 | 248 | 65% | |
Number of PPC405s: | 0 | 1 | 0% | |
Number of Block RAMs: | 19 | 44 | 43% | |
Number of GCLKs: | 5 | 16 | 31% | |
Number of DCMs: | 1 | 4 | 25% | |
Number of GTs: | 0 | 8 | 0% | |
Number of GT10s: | 0 | 0 | 0% |
Property | Value |
Final Timing Score: | 0 |
Number of Unrouted Signals: | All signals are completely routed. |
Number of Failing Constraints: | 0 |
Constraint(s) | Requested | Actual | Logic Levels |
All Constraints Met |
Report Name | Status | Last Date Modified |
Synthesis Report | Current | Thursday 08/25/05 at 15:00 |
Translation Report | Current | Thursday 08/25/05 at 15:00 |
Map Report | Current | Thursday 08/25/05 at 15:01 |
Pad Report | Current | Thursday 08/25/05 at 15:01 |
Place and Route Report | Current | Thursday 08/25/05 at 15:02 |
Post Place and Route Static Timing Report | Current | Thursday 08/25/05 at 15:02 |
Bitgen Report | Current | Thursday 08/25/05 at 15:03 |