| Property | Value |
| Project Name: | c:\cms\firmware\luminosity\htr\v2 |
| Target Device: | xc2v3000 |
| Report Generated: | Wednesday 07/06/05 at 00:14 |
| Printable Summary (View as HTML) | top_summary.html |
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops: | 7,660 | 28,672 | 26% | |
| Number of 4 input LUTs: | 12,023 | 28,672 | 41% | |
| Logic Distribution: | ||||
| Number of occupied Slices: | 10,288 | 14,336 | 71% | |
| Number of Slices containing only related logic: | 10,288 | 10,288 | 100% | |
| Number of Slices containing unrelated logic: | 0 | 10,288 | 0% | |
| Total Number 4 input LUTs: | 15,381 | 28,672 | 53% | |
| Number used as logic: | 12,023 | |||
| Number used as a route-thru: | 1,028 | |||
| Number used for 32x1 RAMs: | 2,112 | |||
| Number used as Shift registers: | 218 | |||
| Number of bonded IOBs: | 486 | 684 | 71% | |
| Number of Block RAMs: | 94 | 96 | 97% | |
| Number of GCLKs: | 8 | 16 | 50% | |
| Number of DCMs: | 1 | 12 | 8% |
| Property | Value |
| Final Timing Score: | 190 |
| Number of Unrouted Signals: | All signals are completely routed. |
| Number of Failing Constraints: | 0 |
| Constraint(s) | Requested | Actual | Logic Levels |
| * TS_clk0_1 = PERIOD TIMEGRP "clk0_1" TS_TTC_CK40Des1 HIGH 50% | 24.000ns | 23.889ns | 13 |
| Report Name | Status | Last Date Modified |
| Synthesis Report | Current | Tuesday 07/05/05 at 17:43 |
| Translation Report | Current | Wednesday 07/06/05 at 00:03 |
| Map Report | Current | Wednesday 07/06/05 at 00:04 |
| Pad Report | Current | Wednesday 07/06/05 at 00:12 |
| Place and Route Report | Current | Wednesday 07/06/05 at 00:12 |
| Post Place and Route Static Timing Report | Current | Wednesday 07/06/05 at 00:13 |
| Bitgen Report | Current | Wednesday 07/06/05 at 00:14 |