| Property | Value |
| Project Name: | c:\cms\firmware\luminosity\sandwich\v8 |
| Target Device: | xc2vp7 |
| Report Generated: | Friday 08/12/05 at 17:55 |
| Printable Summary (View as HTML) | SandwichTop_summary.html |
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops: | 848 | 9,856 | 8% | |
| Number of 4 input LUTs: | 815 | 9,856 | 8% | |
| Logic Distribution: | ||||
| Number of occupied Slices: | 866 | 4,928 | 17% | |
| Number of Slices containing only related logic: | 866 | 866 | 100% | |
| Number of Slices containing unrelated logic: | 0 | 866 | 0% | |
| Total Number 4 input LUTs: | 1,158 | 9,856 | 11% | |
| Number used as logic: | 815 | |||
| Number used as a route-thru: | 343 | |||
| Number of bonded IOBs: | 163 | 248 | 65% | |
| Number of PPC405s: | 0 | 1 | 0% | |
| Number of Block RAMs: | 3 | 44 | 6% | |
| Number of GCLKs: | 4 | 16 | 25% | |
| Number of DCMs: | 1 | 4 | 25% | |
| Number of GTs: | 0 | 8 | 0% | |
| Number of GT10s: | 0 | 0 | 0% |
| Property | Value |
| Final Timing Score: | 0 |
| Number of Unrouted Signals: | All signals are completely routed. |
| Number of Failing Constraints: | 0 |
| Constraint(s) | Requested | Actual | Logic Levels |
| All Constraints Met |
| Report Name | Status | Last Date Modified |
| Synthesis Report | Current | Friday 08/12/05 at 17:52 |
| Translation Report | Current | Friday 08/12/05 at 17:53 |
| Map Report | Current | Friday 08/12/05 at 17:53 |
| Pad Report | Current | Friday 08/12/05 at 17:54 |
| Place and Route Report | Current | Friday 08/12/05 at 17:54 |
| Post Place and Route Static Timing Report | Current | Friday 08/12/05 at 17:54 |
| Bitgen Report | Current | Friday 08/12/05 at 17:55 |