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Signals index

ack : fifo_read2 : output reg

Connects up to:

tb:FIFO:fifo_new_data

ack1 : mbus_data_cycle : wire

bstate : mbus_data_cycle : reg
bstate1 : mbus_data_cycle : reg

clock : fifo_read2 : input (used in @posedge)

Connects up to:

tb:FIFO:clock

clock : mbus_data_cycle : input (used in @posedge)

Connects up to:

tb:CYCLE:clock

clock : tb : reg (used in @posedge)

Connects down to:

fifo_read2:FIFO:clock , mbus_data_cycle:CYCLE:clock

ddone : mbus_data_cycle : wire
done : mbus_data_cycle : output reg

Connects up to:

tb:CYCLE:done

done : tb : wire

Connects down to:

mbus_data_cycle:CYCLE:done

dstrobe : mbus_data_cycle : reg
dstrobe : tb : reg

enable : fifo_read2 : input

Connects up to:

tb:FIFO:fifo_read_edge

enable : mbus_data_cycle : input

Connects up to:

tb:CYCLE:enable

enable : tb : reg

Connects down to:

mbus_data_cycle:CYCLE:enable

enable1 : mbus_data_cycle : reg
end_wire : mbus_data_cycle : wire

fifoscbus : tb : reg

Connects down to:

fifo_read2:FIFO:fifo_scbits

fifo_data : fifo_read2 : input

Connects up to:

tb:FIFO:fifo_data

fifo_data : tb : reg

Connects down to:

fifo_read2:FIFO:fifo_data

fifo_new_data : mbus_data_cycle : input

Connects up to:

tb:CYCLE:fifo_new_data

fifo_new_data : tb : wire

Connects down to:

fifo_read2:FIFO:ack , mbus_data_cycle:CYCLE:fifo_new_data

fifo_read_edge : mbus_data_cycle : output wire

Connects up to:

tb:CYCLE:fifo_read_edge

fifo_read_edge : tb : wire

Connects down to:

fifo_read2:FIFO:enable , mbus_data_cycle:CYCLE:fifo_read_edge

fifo_scbits : fifo_read2 : input

Connects up to:

tb:FIFO:fifoscbus

fstate : fifo_read2 : output reg

Connects up to:

tb:FIFO:fstate

fstate : tb : wire

Connects down to:

fifo_read2:FIFO:fstate

mbus_ack : mbus_data_cycle : input

Connects up to:

tb:CYCLE:mbus_ack

mbus_ack : tb : wire

Connects down to:

mbus_data_cycle:CYCLE:mbus_ack

mbus_data : fifo_read2 : output reg

Connects up to:

tb:FIFO:mbus_data

mbus_data : tb : wire

Connects down to:

fifo_read2:FIFO:mbus_data

mbus_strobe : mbus_data_cycle : output wire

Connects up to:

tb:CYCLE:mbus_strobe

mbus_strobe : tb : wire

Connects down to:

mbus_data_cycle:CYCLE:mbus_strobe

next1 : mbus_data_cycle : reg
nextstate : mbus_data_cycle : reg
n_fstate : fifo_read2 : reg

once : mbus_data_cycle : input

Connects up to:

tb:CYCLE:once

once : tb : reg

Connects down to:

mbus_data_cycle:CYCLE:once

r1 : tb : reg
r2 : tb : reg
r3 : tb : reg
rclk : fifo_read2 : output reg

Connects up to:

tb:FIFO:rclk

rclk : tb : wire (used in @posedge)

Connects down to:

fifo_read2:FIFO:rclk

ren : fifo_read2 : output reg

Connects up to:

tb:FIFO:ren

ren : tb : wire

Connects down to:

fifo_read2:FIFO:ren

resetn : fifo_read2 : input (used in @negedge)

Connects up to:

tb:FIFO:resetn

resetn : mbus_data_cycle : input (used in @negedge)

Connects up to:

tb:CYCLE:resetn

resetn : tb : reg (used in @negedge)

Connects down to:

fifo_read2:FIFO:resetn , mbus_data_cycle:CYCLE:resetn

scbits : fifo_read2 : output reg

Connects up to:

tb:FIFO:scbits

scbits : mbus_data_cycle : input

Connects up to:

tb:CYCLE:scbits

scbits : tb : wire

Connects down to:

fifo_read2:FIFO:scbits , mbus_data_cycle:CYCLE:scbits

Signals

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Created:

Sun Feb 4 08:55:41 2001

Verilog converted to html by v2html 6.0 (written by Costas Calamvokis).

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