//
//
// this module's state machine will look for an enable.  if it's there,
// it will then do 2 fifo reads to make 128 bits, send it via mbus.
// when it gets the EOE marker from the scbits, it'll set it's done
// flag and wait.
//
// enable is an edge
// done is an edge
// fifo_new data is an edge we need to see that there's fifo data.
// it has to be there 1 clock cycle after we hit the fifo_read_edge button,
// which is ok since fifo_input_1 takes about 3 clock cycles or so

`define LOW64_1 	32'h03020100
`define LOW64_2 	32'h07060504
`define HIGH64_1    32'h0B0A0908
`define HIGH64_2    32'h0F0E0D0C


module mbus_data_cycle (
	// inputs
	clock,
	resetn,
	enable,
//	fifo_data,
//	fifoscbus,
	mbus_ack,
	fifo_new_data,
	once,
	scbits,
	// outputs
	fifo_read_edge,
	mbus_strobe,			// this is "dstrobe"
//	mux,
//	mbus_data,
	done,
//	latch_data,
//	scbits
//	strobe_state,
//	end_event
	);


input clock;
input resetn;		//active low
input enable;		
//input[63:0] fifo_data;
//input[1:0] fifoscbus;	
input[1:0] scbits;
input mbus_ack;
input fifo_new_data;
input once;	
output fifo_read_edge;		//	reg fifo_read_edge;
output mbus_strobe;			//	reg mbus_strobe;
//output latch_data;
//output end_event;
//output mux;
//reg end_event;
output done;					reg done;
//output[127:0] mbus_data;		reg[127:0] mbus_data;
//output[1:0] scbits;
//output strobe_state;
//output[3:0] enstate;
//output[3:0] bstate;
//reg[3:0] bstate , nextstate;
//output[12:0] bstate;
//reg[12:0] bstate , nextstate;		//one-hot encoded
//reg[3:0] bstate, nextstate;			//not one-hot encoded

reg dstrobe;
reg enable1;
wire ack1;
wire ddone;
wire mbus_strobe;
wire fifo_read_edge;
assign ddone = mbus_ack;
assign mbus_strobe = dstrobe & ~ddone;
assign fifo_read_edge = enable1 & ~fifo_new_data & ~ack1;
assign ack1 = fifo_new_data;
reg[2:0] bstate1, next1;
parameter[2:0] WAIT1=0, FIFO=1, W_FIFO2=2, ACK=3, W_CLEAR1=4;
/*reg[3:0] bstate, nextstate;
parameter[3:0] WAITD=0, S_ENABLE=1, W_ACK=2, C_ENABLE=3,
	CHECK_END=4, S_DSTROBE=5, W_DDONE=6, C_DSTROBE=7,
	S_DONE=8, WAIT_CLEAR=9;

reg[8:0] bstate, nextstate;
parameter[8:0] WAITD=0, S_ENABLE=1, W_ACK=2, C_ENABLE=4,
	CHECK_END=8, S_DSTROBE=9'h10, W_DDONE=9'h20, C_DSTROBE=9'h40,
	S_DONE=9'h80, WAIT_CLEAR=9'h100;
*/
/*reg[6:0] bstate, nextstate;
parameter[6:0] WAITD=0, W_ACK=1, 
	CHECK_END=2, S_DSTROBE=4, W_DDONE=8, C_DSTROBE=16,
	S_DONE=32, WAIT_CLEAR=64;
*/
reg[2:0] bstate, nextstate;
parameter[2:0] WAITD=0, W_ACK=1, 
	CHECK_END=2, S_DSTROBE=3, W_DDONE=4, C_DSTROBE=5,
	S_DONE=6, WAIT_CLEAR=7;
//reg mux;
//reg strobe_state;
//reg[1:0] scbits;
//reg latch_data;
wire end_wire = scbits[1] | scbits[0];
//always @ (posedge clock or negedge resetn)
//	if (~resetn) end_event <= #1 0;
//	else case (bstate) 
//		WAITD:		end_event <= #1 0;
//		S_DONE:		end_event <= #1 1;
//		default:	end_event <= #1 end_event;
//	endcase


//reg ack1;

/*always @ (posedge clock or negedge resetn)
	if (~resetn) ack1 <= 0;
	else case (bstate1)
		WAIT1:		ack1 <= 0;
//		ACK:		ack1 <= 1;
		W_CLEAR1:		ack1 <= 1;
		default:	ack1 <= ack1;
	endcase
*/
always @ (posedge clock or negedge resetn)
	if (~resetn) enable1 <= 0;
	else case (bstate)
		WAITD:		enable1 <= 0;
//		S_ENABLE:	enable1 <= 1;
		W_ACK:	enable1 <= 1;
//		C_ENABLE:	enable1 <= 0;
		CHECK_END:	enable1 <= 0;
		default:	enable1 <= enable1;
	endcase

always @ (posedge clock or negedge resetn)
	if (~resetn) bstate <= #1 WAITD;
	else bstate <= #1 nextstate;

always @ (bstate or enable or mbus_ack or end_wire or once or ack1)
	case (bstate)
		WAITD: 
			if (enable) nextstate = #1 W_ACK;
//			if (enable) nextstate = S_ENABLE;
			else nextstate = WAITD;
//		S_ENABLE:
//			nextstate = W_ACK;
		W_ACK:
//			if (ack1) nextstate = C_ENABLE;
			if (ack1) nextstate = #1 CHECK_END;
			else nextstate = #1 W_ACK;
//		C_ENABLE:
//			nextstate = CHECK_END;
		CHECK_END: 
			if (end_wire) nextstate = #1 S_DONE;
			else nextstate = #1 S_DSTROBE;
		S_DONE: 
			nextstate = #1 WAIT_CLEAR;
		S_DSTROBE: 
			nextstate = #1 W_DDONE;
		W_DDONE: 
			if (mbus_ack) nextstate = #1 C_DSTROBE;
			else nextstate = #1 W_DDONE;
		C_DSTROBE: 
			if (once) nextstate = #1 S_DONE;
//			else nextstate = S_ENABLE;
			else nextstate = #1 W_ACK;
		WAIT_CLEAR: 
			if (enable) nextstate = #1 WAIT_CLEAR;
			else nextstate = #1 WAITD;
		default: 
			nextstate = #1 WAITD;
	endcase

/*always @ (posedge clock or negedge resetn)
	if (~resetn) bstate1 <= #1 WAIT1;
	else bstate1 <= #1 next1;

always @ (bstate1 or enable1 or fifo_new_data)
	case (bstate1)
		WAIT1: 
//			if (enable1) next1 = FIFO;
			if (enable1) next1 = W_FIFO2;
			else next1 = WAIT1;
//		FIFO: 
//			next1 = W_FIFO2;
		W_FIFO2: 
//			if (fifo_new_data) next1 = ACK;	
			if (fifo_new_data) next1 = W_CLEAR1;	
			else next1 = W_FIFO2;
//		ACK:
//			next1 = W_CLEAR1;
		W_CLEAR1:
			if (enable1) next1 = W_CLEAR1;
			else next1 = WAIT1;
		default: 
			next1 = WAIT1;
	endcase
*/
//
// set fifo_read_edge
//
/*always @ (posedge clock or negedge resetn)
	if (~resetn) fifo_read_edge <= #1 0;
	else case (bstate1)
		WAIT1: 		fifo_read_edge <= #1 0;
		FIFO: 		fifo_read_edge <= #1 1;
//		ACK:	 	fifo_read_edge <= #1 0;
		W_CLEAR1:	 	fifo_read_edge <= #1 0;
		default: 	fifo_read_edge <= #1 fifo_read_edge;
	endcase
*/
//
// set mbus_strobe
//
always @ (posedge clock or negedge resetn)
/*	if (~resetn) mbus_strobe <= 0;
	else case (bstate)
		WAITD:		mbus_strobe <= #1 0;
		S_DSTROBE: 	mbus_strobe <= #1 1;
		C_DSTROBE: 	mbus_strobe <= #1 0;
		default: 	mbus_strobe <= #1 mbus_strobe;	 */
	if (~resetn) dstrobe <= 0;
	else case (bstate)
		WAITD:		dstrobe <= #1 0;
		S_DSTROBE: 	dstrobe <= #1 1;
		C_DSTROBE: 	dstrobe <= #1 0;
		default: 	dstrobe <= #1 dstrobe;
	endcase

/*always @ (posedge clock or negedge resetn)
	if (~resetn) strobe_state <= 0;
	else case (bstate)
		WAITD: 		strobe_state <= #1 0;
		S_DSTROBE:	strobe_state <= #1 1;
		C_DSTROBE:	strobe_state <= #1 0;
		default: 
			strobe_state <= #1 strobe_state ;
	endcase
*/
//
// set done
//
always @ (posedge clock or negedge resetn)
	if (~resetn) done <= #1 0;
	else case (bstate)
		WAITD: 		done <= #1 0;
		S_DONE: 	done <= #1 1;
		default: 	done <= #1 done;
	endcase

endmodule