//* This automatically generated file is a part of Verilog testbench.
//*   This file was generated by Active-HDL 4.1 (TB_verilog v.1.1).
//*   Copyright (C) ALDEC Inc.
//* This Verilog file contains the main Test Bench module
//* and is a part of Verilog Testbench for module "mbus_data_cycle"
//* This file was generated on: Thu Jan 18 21:37:38 2001

`timescale 1ns / 1ns
module tb;

//Internal signals declarations:
reg clock;
reg resetn;
reg enable;
reg [63:0]fifo_data;
reg [1:0]fifoscbus;
//reg mbus_ack;
wire fifo_new_data;
reg once;
wire fifo_read_edge;
wire mbus_strobe;
wire [127:0]mbus_data;
wire done;
wire [1:0]scbits;
wire[2:0] fstate;

	fifo_read2 FIFO (
		// inputs
		.clock(clock),
		.resetn(resetn),
		.enable(fifo_read_edge),
		.fifo_data(fifo_data),
		.fifo_scbits(fifoscbus),
		// outputs
		.ack(fifo_new_data),
		.ren(ren),
		.rclk(rclk),
		.mbus_data(mbus_data),
		.scbits(scbits),
		.fstate(fstate)
		);	  

// Unit Under Test port map
	mbus_data_cycle CYCLE (
		.clock(clock),
		.resetn(resetn),
		.enable(enable),
//		.fifo_data(fifo_data),
//		.fifoscbus(fifoscbus),
		.mbus_ack(mbus_ack),
		.fifo_new_data(fifo_new_data),
		.once(once),
		.fifo_read_edge(fifo_read_edge),
		.mbus_strobe(mbus_strobe),
//		.mbus_data(mbus_data),
		.done(done),
		.scbits(scbits));
 

always #5 clock = ~clock;
initial	begin
	clock = 0;		
	enable = 0;	   
	resetn = 0;
	fifo_data = 0;
	fifoscbus = 0;
	once = 0;
	//
	// ok, send an event
	//
	#40 resetn = 1;
	enable = 1;
end

reg r1,r2,r3,dstrobe;
always @ (posedge clock) r1 <= mbus_strobe;
always @ (posedge clock) r2 <= r1;
always @ (posedge clock) dstrobe <= r2;
wire mbus_ack = dstrobe;

always @ (posedge rclk) begin
	if (~ren) fifo_data <= fifo_data + 64'h0101010101010101;
	else fifo_data <= fifo_data; 
	end

endmodule