//
// this module reads the data fifo's twice to build a 128 bit word for mbus broadcast
//


module fifo_read2 (
	// inputs
	clock,
	resetn,
	enable,
	fifo_data,
	fifo_scbits,
	// outputs
	ack,
	ren,
	rclk,
	mbus_data,
	scbits,
	fstate
	);
	
	input clock;		// 80 MHz.  fifo's are cypress CY7C4255-25 40MHz fifo's
	input resetn;		// active low, as usual
	input enable;		// sets this going.  will not be looked at except for once
	input[63:0] fifo_data;	//64 bits of data fifo
	input[1:0] fifo_scbits;	//2 extra bits for EOE stuff
	 
	output ack;			// ack that we've got it
	output ren;			// fifo read enable
	output rclk;		// fifo read clock
	output[127:0] mbus_data;	// this goes onto mbus (or wherever...)
	output[1:0] scbits;
	output[2:0] fstate;
	reg ack;
	reg ren;
	reg rclk;
	reg[127:0] mbus_data;
	reg[1:0] scbits;
	
	reg[2:0] fstate, n_fstate;
	parameter[3:0] WAIT=0, REN=1, RCLK1=2, RCLK0=3, PAUSE=4, RCLK2=5, PAUSE2=6, PAUSE3=7,
		PAUSE4=8;
//	parameter[2:0] WAIT=0, REN=1, RCLK1=2, RCLK0=3, PAUSE=4, RCLK2=5, PAUSE2=6;
//	reg[7:0] fstate, n_fstate;
//	parameter[7:0] WAIT=0, REN=1, RCLK1=2, RCLK0=4, PAUSE=8, RCLK2=16, PAUSE2=32, WCLEAR=64;
//	reg[6:0] fstate, n_fstate;
//	parameter[6:0] WAIT=0, REN=1, RCLK1=2, RCLK0=4, PAUSE=8, RCLK2=16, PAUSE2=32;
	
	always @ (posedge clock or negedge resetn)
		if (~resetn) fstate <= WAIT;
		else fstate <= #1 n_fstate;
			
	always @ (fstate or enable)
		case (fstate)
			WAIT: 
					if (enable) n_fstate = REN;
					else n_fstate = WAIT;
			REN:	n_fstate = RCLK1;
			RCLK1:	n_fstate = RCLK0;
			RCLK0:	n_fstate = PAUSE;
			PAUSE:	n_fstate = RCLK2;
			RCLK2:	n_fstate = PAUSE2;
			PAUSE2:	n_fstate = PAUSE3;
			PAUSE3:	n_fstate = WAIT;
//			WCLEAR:
//					if (enable) n_fstate = WCLEAR;
//					else n_fstate = WAIT;
		endcase
		
	//
	// now set ren and rclk and mux
	//
	always @ (posedge clock or negedge resetn)
		if (~resetn) begin
			ren <= #1 1;
			rclk <= #1 0; 
			mbus_data <= #1 0;
			scbits <= #1 0;
			ack <= #1 0;
			end
		else case (fstate)
			WAIT: begin				 	//0
				ren <= #1 1;
				rclk <= #1 ~rclk;
				ack <= #1 0;
				if (ack) mbus_data[127:64] <= #1 fifo_data[63:0];
				end
			REN:  begin					//1
				ren <= #1 0;
				rclk <= #1 0;
				end
			RCLK1: rclk <= #1 1;	 	//2
			RCLK0: begin	   			 //3
				rclk <= #1 0;
			end	
			PAUSE: begin
				end
			RCLK2: begin
				mbus_data[63:0] <= #1 fifo_data[63:0];				
				scbits[1:0] <= fifo_scbits[1:0];	
				rclk <= #1 1;	   //5
				ack <= #1 1;
			end
			PAUSE2: begin			   //6
				end
			PAUSE3: begin			   //6
//				mbus_data[127:64] <= #1 fifo_data[63:0];
				rclk <= #1 1;
//				rclk <= #1 1;
//				ack <= #1 1;
				end
			default: begin
				ren <= ren;
				rclk <= rclk;
				mbus_data <= mbus_data;
				scbits <= scbits;
				ack <= ack;
				end
			endcase
	
	
	endmodule