//
// this module controls the transmittersfor real output
// "real output" originates in the ALPHA and is sent via programmed I/O (PIO)
// 
// enable is a level, the logical of the 3 possible PIO commands to send BOE,
// data, or EOE.  if high, it causes the state machine to go.  the machine
// will wait at the end for the done to be asserted, then it will reset.  this
// then assumes that when done is asserted, the enable will go away.  
// this way it will not run free
//
// clock is the system clock 80MHz.  the fifo's can run at 40MHz, so we will use
// the system clock and a 2n-state machine that will toggle the clock every other
// state. this way the clock, wen, data, and scd are all in phase.
//
// resetn is active low as usual
//
// 	OUTPUTS
// data, 8 bits, goes to the FIFO which goes to the cypress TX
// scd   1=special character, 0=data
// wen   write enable.  this is high except when we are writing to the fifo
// wclk  always on
//
`define START_CHAR 8'h0  //K28.0 = 0
`define END_CHAR 8'h8    //K23.7 = 8
`define PAD_CHAR 8'h5    //K28.5 = 5
module transmitters_data (
	// inputs
	clock, 
	resetn,
	send_boe,
	send_data,
	send_eoe,
	mbus_data,
	channel_select,
	strobe,
	// outputs
	data1,data2,
	wen1,wen2,
	wclk,
	scd1,scd2,
	ack,
	dstate);

input clock;
input resetn;
input send_boe;
input send_eoe;
input send_data;
input[127:0] mbus_data;
input channel_select;
input strobe;

output [7:0] data1,data2;
output wen1,wen2;
output wclk;
output scd1,scd2;
output ack;		
output[3:0] dstate;

wire enable = send_boe | send_eoe | send_data;
reg wclk;
//
// stuff for data state
//
reg[7:0] data;
reg scd;
reg wen;
reg ack;
//
wire[7:0] data1 = channel_select ? `PAD_CHAR : data ;
wire[7:0] data2 = channel_select ? data : `PAD_CHAR ;
wire scd1 = channel_select ? 1 : scd ;
wire scd2 = channel_select ? scd : 1 ;
wire wen1 = channel_select ? 1 : wen ;
wire wen2 = channel_select ? wen : 1 ;
//
// state machine for output data from mbus transfer (or whatever)
//
reg[3:0] dstate, ndstate;	  
parameter[3:0] WAIT=0, DWAIT=1, WARM=2, DWARM=3,
 BOE=4, DBOE=5, EOE=6, DEOE=7,
 PAD=8, DPAD=9,
 DATA=10,  DDATA=11, CEND=12, DCEND=13;
//
// 16 bit counter
//
reg[3:0] counter;
wire end_condition = (counter == 4'hf); 
always @ (posedge clock or negedge resetn)
//	if (~resetn) dstate <= WAIT;
	if (~resetn) dstate <= PAD;			// send a few pads so we're in synch at reset
	else dstate <= #2 ndstate;

always @ (dstate or send_boe or send_eoe or send_data or enable or end_condition or strobe)
	case (dstate)
		WAIT: ndstate = #2 DWAIT;
		DWAIT: begin
			if (enable) ndstate = #2 WARM;
			else ndstate = #2 WAIT;
			end
		WARM: ndstate = #2 DWARM;
		DWARM: begin		// sequential logic - priority given to BOE, DATA, EOE in that order		
			if (send_boe) ndstate = #2 BOE;
			else if (send_data) ndstate = #2 DATA;
			else if (send_eoe) ndstate = #2 EOE;
			else ndstate = #2 WAIT;
			end
		BOE: ndstate = #2 DBOE;
		DBOE: begin
			if (send_data) ndstate = #2 DATA;
			else ndstate = #2 PAD;
			end
		EOE: ndstate = #2 DEOE;
		DEOE: ndstate = #2 PAD;
		DATA: ndstate = #2 DDATA;
		DDATA: begin
			if (end_condition) ndstate = #2 CEND;
			else ndstate = #2 DATA;
			end
		CEND: ndstate = #2 DCEND;
		DCEND: begin
			if (send_eoe) ndstate = #2 EOE;
			else ndstate = #2 PAD;
			end
		PAD: ndstate = #2 DPAD;
		DPAD: begin
			if (~strobe) ndstate = #2 WAIT;
			else ndstate = #2 PAD;
			end
		default: ndstate = #2  WAIT;	
	endcase
//
// set wen, data, and sc/d for test data.  note that this will
// keep the clock wclk running.  the data mode will not have to worry
// about the clock wclk, since it will be in synch with this state machine
//
//
// set wen, data, and sc/d for data	mode.  
//
always @ (posedge clock or negedge resetn)
	if (~resetn) begin
		data <= `PAD_CHAR;
		scd <= 1;
		wen <= 1;
		ack <= 0;
		wclk <= 0;
		counter <= 4'h0;
		end
	else case (dstate)
		WAIT: begin
			data <= #2  `PAD_CHAR;
			scd <= #2 1;
			wen <= #2 1;
			ack <= #2 0;
			wclk <= #2 0;
			end
		DWAIT: wclk <= #2 1;
		WARM: begin
			wen <= #2 0;
			wclk <= #2 0;
			end
		DWARM: wclk <= #2 1;
		BOE: begin
			scd <= #2 1;
			wen <= #2 0;
			data <= `START_CHAR;
			wclk <= #2 0;
			end 
		DBOE: wclk <= #2 1;
		EOE: begin
			scd <= #2 1;
			wen <= #2 0;
			data <= `END_CHAR;
			wclk <= #2 0;
			end 
		DEOE: wclk <= #2 1;
		DATA: begin
			wen <= #2 0;
			scd <= #2 0;
			case (counter)
				4'h0: 	data <= mbus_data[7:0];
				4'h1:	data <= mbus_data[15:8]; 
				4'h2:	data <= mbus_data[23:16]; 
				4'h3:	data <= mbus_data[31:24]; 
				4'h4:	data <= mbus_data[39:32];
				4'h5:	data <= mbus_data[47:40];
				4'h6:	data <= mbus_data[55:48];
				4'h7:	data <= mbus_data[63:56];
				4'h8:	data <= mbus_data[71:64];
				4'h9:	data <= mbus_data[79:72];
				4'ha:	data <= mbus_data[87:80];
				4'hb:	data <= mbus_data[95:88];
				4'hc:	data <= mbus_data[103:96];
				4'hd:	data <= mbus_data[111:104];
				4'he:	data <= mbus_data[119:112];
				4'hf:	data <= mbus_data[127:120];
			endcase
			wclk <= #2 0;
			end
		DDATA: begin
			counter <= counter + 1;
			wclk <= #2 1;
			end
		PAD: begin
			wen <= #2 0;
			scd <= #2 1;
			data <= #2 `PAD_CHAR;
			wclk <= #2 0;
			ack <= #2 1;	
			end
		DPAD: wclk <= #2 1;
		default: begin
			data <= #2 data;
			scd <= #2 scd;
			wen <= #2 wen;
			ack <= #2 ack;
			end	
	endcase

endmodule