Hcal Trigger Test mezzanine board (a.k.a. "sandwich board")
Initial Specifications


The mezzanine board should be mounted on the HTR motherboard, on one of the SLB-posts. It allows to plug on top of it the Vitesse Receiver Mezzanine from the Wisconsin RCT group.

FPGA: we have selcted  the XC2VP7-5FG456CES. This part should allow to connect all the lines to/from the HTR and the Vitesse Receiver Mezzanine.
The lines connected to the Vitesse Receiver Mezzanine are 120Mb/s and should be carefully routed.

CLOCK SCHEME: the clock input from the motherboard is 40 MHz 3.3V-PECL;  we have to generate a 3x differential clock for the Vitesse mezzanine.  The XC2VP7 accept only 2.5V-PECL. We can do a series like that:
    RX_CLK_P/N from HTR --> passive network as on Fig4 of XAPP696  -->  XC2VP7  --> CMOS signal to MC100EPT22 --> Vitesse mezzanine REFCLKP/N (each wire need a 140-ohm bias resistor to GND).
Routing of the clock lines: the differential lines should have equal length, the single-ended lines should be very short.
From the motherboard there is another clock line named TTC_CLK or CLK40DES* to be connected directly to a single-ended clock input of the FPGA.

OUTPUTS:
A 40 Mbps signal ("L1A") from the Virtex2Pro; we want to convert it to differential 3.3V-LVPECL - 2 pairs - It's impossible within the Virtex2Pro (it is 2.5V), so the Virtex2Pro  output is a LVTTL, externally converted to 3.3V-LVPECL with discrete translator chips (for example, MC100EPT22 or MC100LVELT22 with both input tied together).
One pair goes to an RJ45 (on the other side of the cable there are 3.3V-LVPECL inputs of a Spartan 2E with a 100-ohm parallel resistor). Each wire need a 140-ohm bias resistor to GND. Possibly the unused pins of the RJ45 should be connected to test points.
On the other pair, the "plus" side will go to a LEMO (on the other side of the cable there is an AC-coupled ECL input - bias ?) ; the "minus" side will  be terminated to gnd  through 140-ohm.
A miniature "D" connector (or any high-speed connector) will be connected directly to the high speed SERDES (Rocket IO) of the XC2VP7-5FG456CES.
There is no need to align the connectors to the HTR front-panel.

EPROM: If using a xilinx PROM, there are control lines to select different revisions of the bitstream. They should be controllable by the motherboard, otherwise by manual settings.

TESTABILITY FEATURES: Test points on GND, Vcc, some FPGA pins. Consider "SMD test points" that is just pads, to avoid taking space in the internal layers. Maybe a connector for the logic analyzer, if it does not disturb a good routing of the other lines.


Board design by EDG.

Tullio Grassi - July 2004
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