`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 02/05/2024 01:57:20 PM
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
`include "include.v"

module autocorrelator (
    input clock,
    input reset,
    input enable,
    input adc,
    input [15:0] sum_id,
    output [`SUM_WIDTH-1:0] sum_out
    );
    
    integer i;
    reg [`SUM_WIDTH-1:0] sums[0:`STAGES-1];
    assign sum_out = sums[sum_id[9:0]];
    reg [`STAGES-1:0] shift;
    always @ (posedge clock)
        if (reset) begin
            shift <= 0;
            for (i=0; i<`STAGES; i=i+1) begin
                sums[i] <= 0;
            end
        end
        else begin
            if (enable) begin
                shift[0] <= adc;
                for (i=0; i<`STAGES-1; i=i+1) begin
                    shift[i+1] <= shift[i];
                    sums[i] = sums[i] + (shift[0] & shift[i]);
               end
            end
        end
endmodule