Introduction to Data Acquisition

Professor Drew Baden: x56069, Web site, email

This is a 3 credit lab/lecture course intended to generate familiarity with the guts of a modern Data Aquisition (DAQ) system, which is composed of processors and FPGAs (field programmagle gate arrays). For processors, we will use a Raspberry PI model 3B+:

which costs around $35 on the Adafruit and other sites.

For the FPGA we will use what is called a "development" board, something that a company builds that makes it easy to use the FPGA for testing etc. The one we will use is a Digilent Basys3 board that has an FPGA made by Xilinx, which was recently bought by AMD.

The first part of the course will consist of lectures, where the student will learn boolean logic, how to build various digital circuits, finite state machines, and programmable logic using the high definition language (HDL) called Verilog.

Following these preliminaries, in the lab part of the course the student will learn how to use the Xilinx program Vivado to program the FPGA, how to build a serial IO connection with a computer, and how to connect to a Raspberry PI.

After some lectures, there will be several labs towards the end of the course. When the student finishes, he/she will be familiar with how to use this equipment to set up an inexpensive but powerful data acquisition system that they can tailor the way they want it.

The course location will be in PHY 3321 (Toll building) and sometimes in PSC 3204.

Lecture: Friday, 2-2:50pm

Lab: Thursday, 2-5:20pm

Course Links

Lecture notes will be available here:

• Lecture 1: Introduction, boolean algebra
• Lecture 2: Networks of gates, binary/hex/octal representations, binary arithmetic
• Lecture 3: Binary adders
• Lecture 4: Other primitives, intro to memory
• Lecture 5: Latches, DFF's, intro to synchronous logic
• Lecture 6: Clock dividers, counters, shift registers
• Lecture 7: Finite state machines
• Lecture 8: Introduction to programmable logic
• Lecture 9: Verilog
• Lecture 10: Verilog FSM
• Lecture 11: Serial communication
• Lecture 12: Verilog test bench

Links to various codes and "how to's" will be available here:

• Download Vivado 2023.1
• Using Vivado 2023.1 to create a traffic light project
• BASYS3 FPGA Input/Output
• LED blinking and Counting Projects
• Programming FLASH RAM
• FPGA<->FPGA-Computer (PC) Serial Communication
• How to set up a Raspberry PI
• FPGA<->FPGA-RPI Serial Communication
• Logic Analyzer (for Debugging)
• Using the FPGA ADC
• Voltmeter: FPGA and RPi
• Voltmeter2: RPi Initiator
• Clocks and FIFOs
• Digital Oscilloscope
• Increasing Bandwidth
• Audio Autocorrelator
• Waveform generator using PWM

Honor Code

It goes without saying that you are on your honor to play fair and not cheat. And as future engineers, you will find that cheating never works, and people who cheat end up falling behind one way or another eventually. Espcially in engineering! Anyway I don't expect any of you will be dishonest, but I have to pass along the following:

The University of Maryland has a nationally recognized Code of Academic Integrity, administered by the Student Honor Council. This Code sets standards for academic integrity at Maryland for all undergraduate and graduate students. As a student, you are responsible for upholding these standards for this course. It is very important for you to be aware of the consequences of cheating, fabrication, facilitating academic dishonesty, and plagiarism. Violations will be taken very seriously and may result in an XF grade for the course and possible suspension. For more information on the Code of Academic Integrity or the Student Honor Council, please visit http://www.shc.umd.edu/.

Religious observances

If you need to miss class, a deadline, or an exam due to a religious observance, please notify me in advance, preferably at the beginning of the semester.

Students with disabilities and/or special needs

Accommodations will be provided to enable students with documented disabilities to participate fully in the course. Please discuss any needs with me at the beginning of the semester so that appropriate arrangements can be made. Students who are registered with DSS, and who are planning to take examinations at DSS facilities, are required to let me have the pertinent authorization forms in editable electronic format at least one week prior to each exam date.

Weather and emergency closures

If the University is closed due to inclement weather or some emergency situation on the scheduled date of an exam, then the exam will be given during the next class period when the University is open. If the University is closed on any non-exam day, including just before an exam, then the exam will still be given according to the original schedule. In these or other exceptional circumstances, I will attempt to send out information by email.

Course announcements by email and email usage

I will be sending important announcements to the class, specifically to each student’s umd.edu email address, as reported to me by the UMEG system, which gets your email from when you logged into Testudo (or from terpmail if you did not specify it with Testudo). If you use some other email system, please make sure that mail sent to your umd.edu address is successfully forwarded to the address you use most regularly. If you have a question, and you can’t get to the TA or to my office hour, then you can send it to me via email. I will respond as soon as I can.

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