From drew@physics.umd.edu Mon Jan 26 18:02:24 2004
Date: Mon, 26 Jan 2004 17:02:48 -0500
From: Drew Baden <drew@physics.umd.edu>
To: 'Richard Kellogg' <richard.kellogg@cern.ch>, HCALELEC@LISTSERV.FNAL.GOV
Cc: drew@physics.umd.edu, tullio@glue.umd.edu
Subject: RE: clock stability studies in bat 28 at CERN (preliminary)


> On Jan 26, 2004, at 20:25, Theresa M. Shaw wrote:
>
> > I would once again surmise that there is a problem with 
> > the clock being supplied to the HTR. 
   [~80MHz GTX_CLK of TI available on test point J10, named
    CLOCK 80 TP on the top side of HTR]
> > It must be an "exactly" double the frequency of the
> > clock being supplied to the FE.  If it is not, things don't work.
> > -Terri


so, we need to verify how the system is setup.  this means checking:

1. the jumper on the HTRs, located right between the MPO connectors.
this jumper selects whether or not the HTRs are using the incoming
80MHz, or the one from the onboard crystal oscillator, for the TLK
reference clock [GTX_CLK]

2. the firmware version of the HTRs

3. the fanout board - what are the piggy back boards that are being
used, and what jumpers are on or off...
There are some fanout boards that have a dual piggy back, then there
are
some that have 3 (including the TTC_UMD board).  and there are some
fanouts that have the QPLL but i'm not sure which you are using.

4. fanout board cabling - are there cables going into the top RJ45
connector?  if so, this would be bringing the clock into the fanout
from the piggyback board setup.
 
5. i forget - are you using the TTCex?  or TTCvx?  i think ex,
but i want to be sure.  also, what is the ultimate source of the
TTC clock?  is it the princeton clock board?  if so, then there
must be an output going into the TTCex.  is this output the right
frequency?  i remember that even if you put a clock into these
TTCex/vx boards, if it's not the right frequency, then the board
uses the onboard "LHC" clock and ignores it.  there are several
ways to check this.
...
drew

> -----Original Message-----
> From: owner-hcalelec@LISTSERV.FNAL.GOV 
> [mailto:owner-hcalelec@LISTSERV.FNAL.GOV] On Behalf Of Richard Kellogg
> Sent: Monday, January 26, 2004 1:42 PM
> To: HCALELEC@LISTSERV.FNAL.GOV
> Cc: Richard Kellogg
> Subject: clock stability studies in bat 28 at CERN (preliminary)
> 
> Dear HCAL electricians,
> 
> Apologies to all those in the US who should have gotten all 
> this information more coherently bright and early this 
> morning.  Getting the pictures on the web and discussing the 
> data just didn't get done in the right order.  Then it was 
> time to go home.
> 
> You can find the scope traces of our studies under:
> 
> http://cms-hcal-installation.web.cern.ch/cms-hcal-installation/
> eye_patterns.html
> 
> It would appear from this evidence that the major jitter 
> (beyond 200ps) enters between the backplane and the optical 
> output of the GOL.  This
> is:
> 
> 1) inconsistent with the fact that the system works fine (and 
> gives a good eye pattern) with the internal oscillator
> 
> 2) contradicts the conclusion we reached while taking the 
> measurements on Friday (which was that the 2nsec rise-time of 
> the signal on the TTC fiber was too slow)
> 
> Jan was of the opinion that 50ps jitter was already 
> sufficient to cause malfunctions, but from the pictures our 
> jitter is WAY beyond that.
> We will discuss possible confusions in the labeling of the 
> pictures tomorrow, and try to arrive at a more coherent 
> analysis.  Kibutzing from the experts in the meantime is 
> welcome, but not required.
> 
>                                          Yours,    Dick
>