HTR VME PRIMER for Altera versions 3E and higher

VME Addressing Scheme

• Interface Registers (VSR)
• Xilinx TOP (XTOP)
• Xilinx BOTTOM (XBOT)
• Flash TOP (FTOP)
• Flash BOTTOM (FBOT)
• Indirect Xilinx TOP (ITOP)
• Indirect Xilinx BOTTOM (IBOT)
• SLB1 through SLB6 (For the testbeam 2003, the SLBs will not be present, so there will be no need to access them over Localbus)

The addressing scheme is described in the following table:

#define HTR_VSR 0x0
#define HTR_XILINX_TOP 0x8000
#define HTR_XILINX_BOT 0x10000
#define HTR_FLASH_TOP 0x20000
#define HTR_FLASH_BOT 0x28000
#define HTR_IND_TOP 0x30000
#define HTR_IND_BOT 0x38000
#define HTR_SLB_1 0x10000   //or equivalently, (SLB+7)<<15 where 1<=SLB<=8 is the SLB number

1. VME Slot: shift 0x4 19 bits to the left
2. Localbus Device: 0x8000
3. Localbus Address: as is

int vme_slot = 4;
int localbus_address = 0x20;
int VME_A = vme_slot<<19 + HTR_XILINX_TOP + localbus_address;

VSR Registers (VME Status Registers)

• Bits 1:0 = 0
• Bits 3:2 contain the current value of the CONFIG_INIT lines. These lines are driven by the TOP (bit 3) and BOTTOM (bit 2) FPGAs during configuration. They should be high except during configuration.
• Bits 5:4 contain the current value of the CONFIG_DONE lines. These lines are driven by the TOP (bit 5) and BOTTOM (bit 4) FPGAs during configuration. They should be high except during configuration

Flash Operations

• Erase Flash
• VME write, Flash Erase
• VME read, Read Data, until data comes back as 0xFF
• VME write, Flash Reset
• VME write, Reset Internal Address Pointer
• For each byte in MCS file:
• Write data into Flash
• VME write, Write Data
• Unlike the firmware for Rev 1 (testbeam 2002), there is no need to issue any of the Flash command sequences such as Address/Data = 0x255/0xaa and so on. This is now being done internally within the HTR ACEX chip.
• Poll for completion by issuing continual VME reads, Read Data. While bit 5 of the value read is not asserted:
• If bit 5 is asserted, a timeout occured. In that case, check bit 8, and if bit 8 read from Flash equals bit 8 of data sent, then write is finished. This can happen when the timeout and successful write condition occur simultaneously. If bit 8 is not asserted, then the write operation failed, and downloading should be aborted and retried.
• While bit 5 is not asserted, check bit 8 (of 8) of data read. If it is equal to data sent, then write is done
• VME write, Increment Internal Address Pointer
• VME write, Reset Internal Address Pointer
• VME write, Reset Internal Address Pointer

Localbus Indirect Addressing Operations

The Localbus inside the HTR is a 21-bit addressable bus. However,the VME address bus is restricted to 24 bits total (A24). In addition, the VME address bits 23:19 are reserved for slot identification, bits 18:15 are reserved for Localbus Device selection, and the bottom 2 bits are off limits since we are running in D32 mode. This leaves only 13 bits (14:2) for legitimate addresses. In order to make an address access that has more than 13 bits, we need another scheme. This is the origin of the indirect addressing in the HTR.

So far (as of 2004) the only "devices" inside the HTR which need more than 13 bits of address space are the Look-up Tables (LUTs) and simulated data rams (RAMS) for injecting data into the front-end of the HTR Xilinx (bypassing the TLK2501 deserializers). These are described below:

Look-up Tables (LUTS)

There are 2 types of LUTS:

• "Input_LUT"

  This LUT converts from 7-bit QIE data format to 10 bit nonlinear plus the muon bit (11 bits total). This LUT will have the pedestal subtraction, linearity, and sin(q) to convert to transverse energy, resulting in a 10-bit number. The 11th bit is a muon feature bit - describes whether the energy is consistent with that from a minimum ionizing muon. Since there are 7 bits in, this LUT is 7-bit addressable. There are 24 of these LUTs, 1 per QIE channel, and the output of these LUTs are used for the TPGs.

• "Output_LUT"

  This LUT converts the energy into a form for sending to the SLB and from there to the Level 1 trigger. Since there are 10 bits in, this LUT needs 10 bits in the address field. There are 24 of these LUTs, 1 per TPG channel.

Injection RAMs (RAMS)

We have the ability to inject data into the HTR to mimic raw data coming up from the Front-end boards. This will allow you to debug without the need of fiber data, if necessary.

There will be 8 RAMS per Xilinx FPGA, 1 per fiber. You write to the indirect address register of the Altera (VSR, see below) (0x28 for TOP and 0x2C for BOT) and in the low 9 bits of the VME data word you put the fiber number (from 0 to 7) + 0x180. The Altera FPGA latches these values. This will tell the Xilinx FPGA which RAM you will be reading from or writing to. Then you write to the relative address (a total of 10 bits, so there are 1024 different RAM addresses).

For example, say you want to read or write to RAM addresses for fiber 2 (8 fibers, 1 to 8) of the TOP Xilinx of the HTR in VME slot 12. The sequence is:

• Write 0x180 + (fiber - 1) = 0x181 to VME address 0x600000 (vme_ slot<<19) + 0x00000 (Localbus device 0, see above) + address 0x28 = 0x600028

Then, to read from or write into any of the 1024 individual RAM addresses, you read/write to that address over VME (shifted over 2 bits to the left) with the indirect device set. So, with the above example already done (writing 0x181 to 0x600028) say you would like to write 0x5432 to RAM address 0xF, you would write the 0x5432 as VME data to VME address 0x600000 + 0x30000 + (0xF <<2) = 0x63003C.

To use this, we suggest the following sequence (which you can do inside htr):

• Reset CSR (0xC) to be safe
  • Write 0x0 to VME address vme_slot<<19 + HTR_XILINX_TOP.or.HTR_XILINX_BOT + 0xC (see above)
  • In htr go into XFPGA menu and do a "write C 0"
• Set the Global Indirect Address (tells the RAM corresponding to the fiber)
  • In htr go into the RAMS menu and just set the fiber, it's done automatically
• Write into the RAMS via indirect addressing:

The following .htr file (htr macro, sent via ./htr -x <file>) will set gaussians to each fiber, with a different gaussian mean and sigma 1 for all 8 fibers, then send a TTC broadcast command ("test") to get things rolling:

   slot 12   #or whatever slot you are working in
   rams
   #fiber 1 gaussian at 3 width 1
   gen 0 3 1
   #fiber 2 gaussian at 6 width 1
   fiber 2
   gen 0 6 1
   #fiber 3 gaussian at 9 width 1
   fiber 3
   gen 0 9 1
   #fiber 4 gaussian at 12 width 1
   fiber 4
   gen 0 12 1
   #fiber 5 gaussian at 15 width 1
   fiber 5
   gen 0 15 1
   #fiber 6 gaussian at 18 width 1
   fiber 6
   gen 0 18 1
   #fiber 7 gaussian at 21 width 1
   fiber 7
   gen 0 21 1
   #fiber 8 gaussian at 24 width 1
   fiber 8
   gen 0 24 1
   # now enabl the rams and put in repeat mode
   control 1 1
   quit
   # now send the ttc command
   ttc
   reset
   bro 20 1
   quit
   quit
  

Indirect Addressing (memory paging)

Since there are 24 LUTs per type, and 2 types ("Input_LUT" and "Output_LUT"), we need at least 6 bits to determine which LUT we are working with. The Output_LUT needs 10 bits for addressing, which makes 16 bits total. This number exceeds the 13 bits available over VME (see above). To get around this limitation, we defined a "global indirect address" to "point" to which LUT or RAM we are working with, then we do the reads and writes using the "indirect address" for the individual LUT or RAM.

Setting the "Global Indirect Address" is done via a write to the VSR space (Localbus Device = 0). For the TOP Xilinx, you write the global address to the register at 0x28 and for the BOT Xilinx, you write to 0x2C. For example, if you wanted to read/write the global indirect address for the TOP HTR in slot 16, the VME address would be:

16<<19 + 0x0 + 0x28 = 0x01000028

Similary for the BOT xilinx (0x0100002C)

Last Update 10Oct2005 Drew Baden