HFT Demo board with two XC2VP40 (RocketIO)

Updated : Oct 27th, 2005 (last changes marked with **)

** This mezzanine board plugs on 3 (or 4?) PMC/SLB posts of the HTR motherboard and must fit the width of one VME slot.
It includes:

1  FPGA for transmission - XC2VP40-FF1152   
1  Am29LV116D PROM (same part and scheme as on HTR) for Tx-FPGA
1  MEG-Array connector FCI PN 84512 for parallel optic transmitter

1  FPGA for reception - XC2VP40-FF1152    
1  Am29LV116D PROM (same part and scheme as on HTR) for Rx-FPGA
1  MEG-Array connector FCI PN 84512 for parallel optic receiver

12 PMC connectors to connect to the motherboard.
1 nonvolatile 3.3V CPLD (e.g. XC95288XL-TQ144) to allow to reprogram the Flash memory over VME/LocalBus.
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** OPTICAL TRANSMITTERS
Picolight; PL-TCP-00-S53 and corresponding receivers PL-RCP-00-S53; compatible with the socket MEG-Array connector FCI PN 84512.

** CLOCKING:
We need two independent clock circuitries for transmitter and receiver, to emulate two separate boards.
Input to the clock pins of the FPGAs should come from:
1) Two mini USB connectors for Clk80, terminated as the signal CLEAN_CLOCK_P/N on the HTR. The pair must connest to the pin pair (GCLK4S, GCLK5P) and to the pin pair (GCLK6P, GCLK7S). We may need a differential fanout chip.
2) Two diff-PECL crystal oscillators (we can reuse the same scheme as in the HTR, if it fits and parts are available). The Rx-crystal will be a little faster than the Tx-crystal. The pair must connect to the pin pair (GCLK2S, GCLK3P) and to the pin pair (GCLK0P, GCLK1S). We may need a differential fanout chip.
3) Two 3.3V-LVDS pairs RX_CLK_*P and RX_CLK_*N from the motherboard, to one of the remaining clock input pair.

CONNECTIVITY
- The 12 TxFPGA pin pairs (TXPPAD*, TXNPAD*) connect to the "Tx" MegArray.
- The 12 RxFPGA pin pairs (RXPPAD*, RXNPAD*) connect to the "Rx" MegArray.
- JTAG connects all FPGAs (short the 2 unused JTAG TDI/TDOs).
- The TxFPGA connects to (some) data lines from the PMC connectors.
- The FPGAs should be connected by several LVDS pairs, with various routing.
- The FPGAs and CPLD have several spare connections.
- ** two more mini USB connect to two differential pin pairs (not clock) of the TxFPGA. - PIN LIST of XC2VP40


POWER
Vcco of FPGAs connected to 2.5V.
See page 109 (Power Conditioning) of RocketIO Transceiver User Guide.


LAYOUT:
Reccomandation: design in metric units for part placement and routing; use a 0.2mm trace and a 0.1mm routing grid and a 1mm placement grid for these BGA's. Use 24/12 via (.024 pad/.012 drill).
The data lines from the PMC connectors to the two Virtex2Pro run at 80 Mb/s. They should have a clean routing with minimal crossing and vias.
Special care for high-speed serial lines to/from the MEG-Array connectors and for the clock lines: max mismatch in length for complementary traces is 1.2 mm. If there are vias on these lines a capacitor of value 0.01 µF should be connected across the two reference layers close to the vias where the signals change layers. Clearance = 5x trace-width. See RocketIO Transceiver User Guide

PROBLEMS:
PCB plating: for BGAs: we had good experience only with gold, while pads for MEG-Array connector should be Copper with OSP or HASL [page 8 of Application Spec on  https://portal.fciconnect.com/res/en/pdffiles/Specs/gs-20-033.pdf ]
Decision: we use gold.

FPGA considerations:
The RocketIO reference clock must be at least 50 MHz and should have a frequency stability of ±100 ppm or better, with jitter as low as possible.

FIRMWARE VERSIONS


CPLD Project
and programming file		 CAD
and O.S.		 FPGAversionN
(hex)		  Notes 
HFTbridge_estim.zip
jed n.a.		 ISE7.1.4 on WinXP n.a. Non functional version.
Used to evaluate logic occupancy on a XC95288XL-6-TQ144: 52% without crc; ~%80 with crc.
This version is a good starting point to get a functional version;
it only tries to write into the Flash memory and configure the FPGA.

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